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29 janvier 2011 6 29 /01 /janvier /2011 12:36

Conventional PCI (PCI is an initialism formed from Peripheral Component Interconnect,part of the PCI Local Busstandard and often shortened toPCI) is a computer bus for attaching hardware devices in a computer   (Dell XPS M1210 Batteryhttp://www.hdd-shop.co.uk .

These devices can take either the form of an integrated circuit fitted onto the motherboard itself, called a planar device in the PCI specification, or an expansion card that fits into a slot. The PCI Local Bus is common in modern PCs, where it has displaced ISA and VESA Local Bus as the standard expansion bus, and it also appears in many other computer types   (Dell Studio XPS 1640 Battery)    .

Despite the availability of faster interfaces such as PCI-X and PCI Express, conventional PCI remains a very common interface.

The PCI specification covers the physical size of the bus (including the size and spacing of the circuit board edge electrical contacts), electrical characteristics, bus timing, and protocols       (Dell Vostro 1710 Battery)        .

The specification can be purchased from the PCI Special Interest Group (PCI-SIG).

Typical PCI cards used in PCs include: network cards, sound cards, modems, extra ports such as USB or serial, TV tuner cards and disk controllers      Dell KM958 battery .

Historically video cards were typically PCI devices, but growing bandwidth requirements soon outgrew the capabilities of PCI. PCI video cards remain available for supporting extra monitors and upgrading PCs that do not have any AGP or PCI Express slots.

Many devices traditionally provided on expansion cards are now commonly integrated onto the motherboard itself, meaning that modern PCs often have no cards fitted      Dell Studio 1555 battery .

However, PCI is still used for certain specialized cards, although many tasks traditionally performed by expansion cards may now be performed equally well by USB devices.


Work on PCI began at Intel's Architecture Development Lab circa 1990     Sony VGP-BPS13 battery .

A team of Intel engineers (composed primarily of ADL engineers) defined the architecture and developed a proof of concept chipset and platform (Saturn) partnering with teams in the company's desktop PC systems and core logic product organizations. The original PCI architecture team included, among others, Dave Carson, Norm Rasmussen, Brad Hosler, Ed Solari, Bruce Young, Gary Solomon, Ali Oztaskin, Tom Sakoda, Rich Haslam, Jeff Rabe, and Steve Fischer      Sony VGP-BPS13/B battery .

PCI (Peripheral Component Interconnect) was immediately put to use in servers, replacing MCA and EISA as the server expansion bus of choice. In mainstream PCs, PCI was slower to replace VESA Local Bus (VLB), and did not gain significant market penetration until late 1994 in second-generation Pentium PCs     Sony VGP-BPS13/S battery .

By 1996 VLB was all but extinct, and manufacturers had adopted PCI even for 486computers. EISA continued to be used alongside PCI through 2000. Apple Computer adopted PCI for professional Power Macintosh computers (replacing NuBus) in mid-1995, and the consumerPerforma product line (replacing LC PDS) in mid-1996       Sony VGP-BPS13A/B battery .

Later revisions of PCI added new features and performance improvements, including a 66 MHz 3.3 V standard and 133 MHz PCI-X, and the adaptation of PCI signaling to other form factors. Both PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards       Sony VGP-BPS13B/B battery .

The PCI-SIG introduced the serial PCI Express in 2004. At the same time they renamed PCI as Conventional PCI. Since then, motherboard manufacturers have included progressively fewer Conventional PCI slots in favor of the new standard.

Auto Configuration           Sony VGP-BPL9 battery

PCI provides separate memory and I/O port address spaces for the x86 processor family, 64 and 32 bits, respectively. Addresses in these address spaces are assigned by software. A third address space, called the PCI Configuration Space, which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device  Sony VGP-BPS13B/B battery .

Each device can request up to six areas of memory space or I/O port space via its configuration space registers.

In a typical system, the firmware (or operating system) queries all PCI buses at startup time (via PCI Configuration Space) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs    Sony VGP-BPL15 battery .

It then allocates the resources and tells each device what its allocation is.

The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration       Dell Inspiron E1505 battery .

Devices may have an on-board ROM containing executable code for x86 or PA-RISC processors, an Open Firmware driver, or an EFI driver. These are typically necessary for devices used during system startup, before device drivers are loaded by the operating system      Dell Latitude E6400 battery .

In addition there are PCI Latency Timers that are a mechanism for PCI Bus-Mastering devices to share the PCI bus fairly. "Fair" in this case means that devices won't use such a large portion of the available PCI bus bandwidth that other devices aren't able to get needed work done. Note, this does not apply to PCI Express         HP Pavilion dv6000 Battery .

How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock        SONY VAIO VGN-FZ Battery .

When the counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data.


Devices are required to follow a protocol so that the interrupt lines can be shared      SONY VAIO VGN-FZ18 Battery .

The PCI bus includes four interrupt lines, all of which are available to each device. However, they are not wired in parallel as are the other PCI bus lines. The positions of the interrupt lines rotate between slots, so what appears to one device as the INTA# line is INTB# to the next and INTC# to the one after that      SONY VAIO VGN-FZ21E Battery .

Single-function devices use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines. This alleviates a common problem with sharing interrupts.

PCI bridges (between two PCI buses) map the four interrupt traces on each of their sides in varying ways    SONY VAIO VGN-FW21E Battery .

Some bridges use a fixed mapping, and in others it is configurable. In the general case, software cannot determine which interrupt line a device's INTA# pin is connected to across a bridge. The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is similarly implementation-dependent       SONY VAIO VGN-NR11S/S Battery .

The result is that it can be impossible to determine how a PCI device's interrupts will appear to software. Platform-specific BIOS code is meant to know this, and set a field in each device's configuration space indicating which IRQ it is connected to, but this process is not reliable      SONY VAIO VGN-NR11M/S Battery .

PCI interrupt lines are level-triggered. This was chosen over edge-triggering in order to gain an advantage when servicing a shared interrupt line, and for robustness: edge triggered interrupts are easy to miss.

Later revisions of the PCI specification add support for message-signaled interrupts        SONY VAIO VGN-NR11Z/S Battery .

In this system a device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines. Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts        SONY VAIO VGN-NR11Z/T Battery .

It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because the message signaling is in-band, it resolves some synchronization problems that can occur with posted writes and out-of-band interrupt lines       Sony VAIO VGN-FZ21E Battery .

PCI Express does not have physical interrupt lines at all. It uses message-signaled interrupts exclusively.

Conventional hardware specifications

Diagram showing the different key positions for 32-bit and 64-bit PCI cards

These specifications represent the most common version of PCI used in normal PCs    Sony VAIO VGN-FW21E Battery .

  • 33.33 MHz clock with synchronous transfers
  • peak transfer rate of 133 MB/s (133 megabytes per second) for 32-bit bus width (33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s)
  • 32-bit bus width
  • 32- or 64-bit memory address space (4 gigabytes or 16 exabytes)        Sony VAIO VGN-NR11S/S Battery
  • 32-bit I/O port space
  • 256-byte (per device) configuration space
  • 5-volt signaling
  • reflected-wave switching         Sony VAIO VGN-NR11Z/S Battery

The PCI specification also provides options for 3.3 V signaling, 64-bit bus width, and 66 MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards.

The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus       Sony VAIO VGN-NR11M/S Battery .

Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master.

Card keying

A PCI-X Gigabit Ethernet expansion card. Note both 5 V and 3.3 V support notches are present   Sony VAIO VGN-NR11Z/T Battery .

Typical PCI cards present either one or two key notches, depending on their signaling voltage. Cards requiring 3.3 volts have a notch 56.21 mm from the front of the card (where the external connectors are) while those requiring 5 volts have a notch 104.47 mm from the front of the card         SONY VAIO VGN-FZ180E Battery .

So called "Universal cards" have both key notches and can accept both types of signal.

Connector pinout

The PCI connector is defined as having 62 contacts on each side of the edge connector, but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side        SONY VAIO VGN-FZ220E Battery .

Pin 1 is closest to the backplate. B and A sides are as follows, looking down into the motherboard connector.

Most lines are connected to each slot in parallel. The exceptions are:

  • Each slot has its own REQ# output to, and GNT# input from the motherboard arbiter.
  • Each slot has its own IDSEL line, usually connected to a specific AD line   SONY VAIO VGN-FZ340E Battery .
  • TDO is daisy-chained to the following slot's TDI. Cards without JTAG support must connect TDI to TDO so as not to break the chain.
  • PRSNT1# and PRSNT2# for each slot have their own pull-up resistors on the motherboard. The motherboard may (but does not have to) sense these pins to determine the presence of PCI cards and their power requirements  SONY VAIO VGN-FZ430E Battery .
  • REQ64# and ACK64# are individually pulled up on 32-bit only slots.
  • The interrupt lines INTA# through INTD# are connected to all slots in different orders. (INTA# on one slot is INTB# on the next and INTC# on the one after that.         SONY VAIO VGN-FZ460E Battery


  • IOPWR is +3.3V or +5V, depending on the backplane. The slots also have a ridge in one of two places which prevents insertion of cards that do not have the corresponding key notch, indicating support for that voltage standard. Universal cards have both key notches and use IOPWR to determine their I/O signal levels     SONY VAIO VGN-FZ480E Battery .
  • The PCI SIG strongly encourages 3.3 V PCI signaling, requiring support for it since standard revision 2.3, but most PC motherboards use the 5 V variant. Thus, while many currently available PCI cards support both, and have two key notches to indicate that, there are still a large number of 5 V-only cards on the market           SONY VAIO VGN-FZ4000 Battery .
  • The M66EN pin is an additional ground on 5V PCI buses found in most PC motherboards. Cards and motherboards that do not support 66 MHz operation also ground this pin. If all participants support 66 MHz operation, a pull-up resistor on the motherboard raises this signal high and 66 MHz operation is enabled        SONY VAIO VGN-FZ31E Battery .
  • At least one of PRSNT1# and PRSNT2# must be grounded by the card. The combination chosen indicates the total power requirements of the card (25 W, 15 W, or 7.5 W).
  • SBO# and SDONE are signals from a cache controller to the current target. They are not initiator outputs, but are colored that way because they are target inputs      SONY VAIO VGN-FZ31B Battery .

Physical card dimensions

Full-size card

The original "full-size" PCI card is specified as a height of 107 mm (4.2 inches) and a depth of 312 mm (12.283 inches). The height includes the edge card connector       SONY VAIO VGN-FZ31J Battery .

However, most modern PCI cards are half-length or smaller (see below) and many modern PCs cannot fit a full-size card.

Card backplate

In addition to these dimensions the physical size and location of a card's backplate are also standardized     SONY VAIO VGN-FZ31M Battery .

The backplate is the part that fastens to the card cage to stabilize the card and also contains external connectors, so it usually attaches in a window so it is accessible from outside the computer case. The backplate is fixed to the cage by a 6-32 screw.

The card itself can be a smaller size, but the backplate must still be full-size and properly located so that the card fits in any standard PCI slot     SONY VAIO VGN-FZ31Z Battery .

Half-length extension card (de-facto standard)

This is in fact the practical standard now – the majority of modern PCI cards fit inside this length.

Low-profile (half-height) card

The PCI organization has defined a standard for "low-profile" cards, which basically fit in the following ranges:

  • Height: 1.42 inches (36.07 mm) to 2.536 inches (64.41 mm)
  • Depth: 4.721 inches (119.91 mm) to 6.6 inches (167.64 mm)       SONY VGP-BPS8 Battery

The bracket is also reduced in height, to a standard 3.118 inches (79.2 mm). The smaller bracket will not fit a standard PC case, but will fit in a 2U rack-mount case. Many manufacturers supply both types of bracket (brackets are typically screwed to the card so changing them is not difficult)       SONY VGP-BPS13 Battery .

These cards may be known by other names such as "slim".

Mini PCI was added to PCI version 2.2 for use in laptops; it uses a 32-bit, 33 MHz bus with powered connections (3.3 V only; 5 V is limited to 100 mA) and support for bus mastering and DMA        SONY VGP-BPS13/S Battery .

The standard size for Mini PCI cards is approximately 1/4 of their full-sized counterparts. As there is limited external access to the card compared to desktop PCI cards, there are limitations on the functions they may perform.

PCI-to-MiniPCI converter Type III        SONY VGP-BPS13A/B Battery

MiniPCI and MiniPCI Express cards in comparison

Many Mini PCI devices were developed such as Wi-Fi, Fast Ethernet, Bluetooth, modems (often Winmodems), sound cards, cryptographic accelerators, SCSI, IDE–ATA, SATA controllers and combination cards       SONY VGP-BPS13B/B Battery .

Mini PCI cards can be used with regular PCI-equipped hardware, using Mini PCI-to-PCI converters. Mini PCI has been superseded by PCI Express Mini Card.

Technical details of Mini PCI       SONY VGP-BPS13A/S Battery

Mini PCI cards have a 2 W maximum power consumption, which also limits the functionality that can be implemented in this form factor. They also are required to support the CLKRUN# PCI signal used to start and stop the PCI clock for power management purposes        SONY VGP-BPS13AS Battery .

There are three card form factors: Type I, Type II, and Type III cards. The card connector used for each type include: Type I and II use a 100-pin stacking connector, while Type III uses a 124-pin edge connector, i.e. the connector for Types I and II differs from that for Type III, where the connector is on the edge of a card, like with a SO-DIMM       Dell Inspiron 1320n Battery .

The additional 24 pins provide the extra signals required to route I/O back through the system connector (audio, AC-Link, LAN, phone-line interface). Type II cards have RJ11 and RJ45 mounted connectors. These cards must be located at the edge of the computer or docking station so that the RJ11 and RJ45 ports can be mounted for external access      Dell Inspiron 1464 Battery .

Type Card on outer edge of host system          Connector        Size  Comments

IA     No    100-Pin Stacking       7.5 × 70 × 45 mm     Large Z dimension (7.5 mm)

IB     No    100-Pin Stacking       5.5 × 70 × 45 mm     Smaller Z dimension (5.5 mm)  Dell Inspiron 1564 Battery

IIA    Yes   100-Pin Stacking       17.44 × 70 × 45 mm          Large Z dimension (17.44 mm)

IIB    Yes   100-Pin Stacking       5.5 × 78 × 45 mm     Smaller Z dimension (5.5 mm)

IIIA   No    124-Pin Card Edge   2.4 × 59.6 × 50.95 mm     Larger Y dimension (50.95 mm)   Dell Inspiron 1764 Battery

IIIB   No    124-Pin Card Edge   2.4 × 59.6 × 44.6 mm       Smaller Y dimension (44.6 mm)

Mini PCI should not be confused with 144-pin Micro PCI.    Dell Studio 1450 Battery

Other physical variations

Typically consumer systems specify "N × PCI slots" without specifying actual dimensions of the space available. In some small-form-factor systems, this may not be sufficient to allow even "half-length" PCI cards to fit   Dell Studio 1457 Battery .

Despite this limitation, these systems are still useful because many modern PCI cards are considerably smaller than half-length.

PCI bus transactions

PCI bus traffic is made of a series of PCI bus transactions. Each transaction is made up of an address phase followed by one or more data phases       Dell Latitude D610 Battery .

The direction of the data phases may be from initiator to target (write transaction) or vice-versa (read transaction), but all of the data phases must be in the same direction. Either party may pause or halt the data phases at any point     Toshiba NB100 Battery .

(One common example is a low-performance PCI device that does not support burst transactions, and always halts a transaction after the first data phase.)

Any PCI device may initiate a transaction. First, it must request permission from a PCI bus arbiter on the motherboard. The arbiter grants permission to one of the requesting devices     Toshiba Satellite M65 battery .

The initiator begins the address phase by broadcasting a 32-bit address plus a 4-bit command code, then waits for a target to respond. All other devices examine this address and one of them responds a few cycles later.

64-bit addressing is done using a two-stage address phase        Toshiba Satellite M60 battery .

The initiator broadcasts the low 32 address bits, accompanied by a special "dual address cycle" command code. Devices which do not support 64-bit addressing can simply not respond to that command code. The next cycle, the initiator transmits the high 32 address bits, plus the real command code       Dell Latitude D830 Battery .

The transaction operates identically from that point on. To ensure compatibility with 32-bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.e. if the high-order address bits are all zero.

While the PCI bus transfers 32 bits per data phase, the initiator transmits a 4-bit byte mask indicating which 8-bit bytes are to be considered significant     Dell Latitude D620 Battery .

In particular, a masked write must affect only the desired bytes in the target PCI device.

PCI address spaces

PCI has three address spaces: memory, I/O address, and configuration       Dell Inspiron Mini 10 Battery .

Memory addresses are 32 bits (optionally 64 bits) in size, support caching and can be burst transactions.

I/O addresses are for compatibility with the Intel x86 architecture's I/O port address space. Although the PCI bus specification allows burst transactions in any address space, most devices only support it for memory addresses and not I/O  Sony VGN-FW11S Battery .

Finally, PCI configuration space provides access to 256 bytes of special configuration registers per PCI device. Each PCI slot gets its own configuration space address range. The registers are used to configure devices memory and I/O address ranges they should respond to from transaction initiators       Sony VGN-FW11M Battery .

When a computer is first turned on, all PCI devices respond only to their configuration space accesses. The computers BIOS scans for devices and assigns Memory and I/O address ranges to them.

If an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation       Sony VGN-FW139E/H battery .

In case of reads, it is customary to supply all-ones for the read data value (0xFFFFFFFF) in this case. PCI devices therefore generally attempt to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software    Dell Latitude E5400 Battery .

PCI command codes

There are 16 possible 4-bit command codes, and 12 of them are assigned. With the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read (data sent from target to initiator) or a write (data sent from an initiator to target)     Dell Latitude E4200 Battery .

PCI targets must examine the command code as well as the address and not respond to address phases which specify an unsupported command code.

The commands that refer to cache lines depend on the PCI configuration space cache line size register being set up properly; they may not be used until that has been done    Dell Inspiron 300M Battery .

0000: Interrupt Acknowledge

This is a special form of read cycle implicitly addressed to the interrupt controller, which returns an interrupt vector. The 32-bit address field is ignored      Dell Vostro A840 Battery .

One possible implementation is to generate an interrupt acknowledge cycle on an ISA bus using a PCI/ISA bus bridge. This command is for IBM PC compatibility; if there is no Intel 8259 style interrupt controller on the PCI bus, this cycle need never be used  Dell Studio 1737 battery .

0001: Special Cycle

This cycle is a special broadcast write of system events that PCI card may be interested in. The address field of a special cycle is ignored, but it is followed by a data phase containing a payload message       Dell Inspiron E1505 battery .

The currently defined messages announce that the processor is stopping for some reason (e.g. to save power). No device ever responds to this cycle; it is always terminated with a master abort after leaving the data on the bus for at least 4 cycles   Dell RM791 battery .

0010: I/O Read

This performs a read from I/O space. All 32 bits of the read address are provided, so that a device can (for compatibility reasons) implement less than 4 bytes worth of I/O registers         Dell XPS M1530 battery .

If the byte enables request data not within the address range supported by the PCI device (e.g. a 4-byte read from a device which only supports 2 bytes of I/O address space), it must be terminated with a target abort. Multiple data cycles are permitted, using linear (simple incrementing) burst ordering        Dell XPS M2010 battery .

The PCI standard is discouraging the use of I/O space in new devices, preferring that as much as possible be done through main memory mapping.

0011: I/O Write

This performs a write to I/O space.

010x: Reserved

A PCI device must not respond to an address cycle with these command codes         Acer Aspire One battery .

0110: Memory Read

This performs a read cycle from memory space. Because the smallest memory space a PCI device is permitted to implement is 16 bits, the two least significant bits of the address are not needed; equivalent information will arrive in the form of byte select signals  Toshiba Satellite P10 Battery .

They instead specify the order in which burst data must be returned. If a device does not support the requested order, it must provide the first word and then disconnect.

If a memory space is marked as "prefetchable", then the target device must ignore the byte select signals on a memory read and always return 32 valid bits       SONY VGN-FZ210CE Battery .

0111: Memory Write

This operates similarly to a memory read. The byte select signals are more important in a write, as unselected bytes must not be written to memory.

Generally, PCI writes are faster than PCI reads, because a device can buffer the incoming write data and release the bus faster   Dell Precision M70 Battery .

For a read, it must delay the data phase until the data has been fetched.

100x: Reserved

A PCI device must not respond to an address cycle with these command codes  Toshiba Satellite L305 Battery .

1010: Configuration Read

This is similar to an I/O read, but reads from PCI configuration space. A device must respond only if the low 11 bits of the address specify a function and register that it implements, and if the special IDSEL signal is asserted. It must ignore the high 21 bits. Burst reads (using linear incrementing) are permitted in PCI configuration space       Toshiba Satellite T4900 Battery .

Unlike I/O space, standard PCI configuration registers are defined so that reads never disturb the state of the device. It is possible for a device to have configuration space registers beyond the standard 64 bytes which have read side effects, but this is rare     Toshiba PA3399U-2BRS battery .

Configuration space accesses often have a few cycles of delay in order to allow the IDSEL lines to stabilize, which makes them slower than other forms of access. Also, a configuration space access requires a multi-step operation rather than a single machine instruction. Thus, it is best to avoid them during routine operation of a PCI device         Toshiba Satellite A200 Battery .

1011: Configuration Write

This operates analogously to a configuration read.

1100: Memory Read Multiple        Toshiba Satellite 1200 Battery

This command is identical to a generic memory read, but includes the hint that a long read burst will continue beyond the end of the current cache line, and the target should internally prefetch a large amount of data . A target is always permitted to consider this a synonym for a generic memory read       Toshiba Satellite M300 Battery .

1101: Dual Address Cycle

When accessing a memory address that requires more than 32 bits to represent, the address phase begins with this command and the low 32 bits of the address, followed by a second cycle with the actual command and the high 32 bits of the address   SONY VGP-BPS13A/Q Battery .

PCI targets that do not support 64-bit addressing can simply treat this as another reserved command code and not respond to it. This command code can only be used with a non-zero high-order address word; it is forbidden to use this cycle if not necessary      SONY VGP-BPS13A/Q Battery .

1110: Memory Read Line

This command is identical to a generic memory read, but includes the hint that the read will continue to the end of the cache line. A target is always permitted to consider this a synonym for a generic memory read         SONY VGP-BPS13B/Q Battery .

1111: Memory Write and Invalidate

This command is identical to a generic memory write, but comes with the guarantee that one or more whole cache lines will be written, with all byte selects enabled. This is an optimization for write-back caches snooping the bus        SONY VGP-BPS13B/Q Battery.

Normally, a write-back cache holding dirty data must interrupt the write operation long enough write its own dirty data first. If the write is performed using this command, the data to be written back is guaranteed to be irrelevant, and can simply be invalidated in the write-back cache       SONY VGP-BPS13/Q Battery .

This optimization only affects the snooping cache, and makes no difference to the target, which may treat this as a synonym for the memory write command.

PCI bus signals

PCI bus transactions are controlled by five main control signals, two driven by the initiator of a transaction (FRAME# and IRDY#), and three driven by the target (DEVSEL#, TRDY#, and STOP#)       SONY VGP-BPS13/Q Battery .

There are two additional arbitration signals (REQ# and GNT#) which are used to obtain permission to initiate a transaction. All are active-low, meaning that the active or asserted state is a low voltage. Pull-up resistors on the motherboard ensure they will remain high (inactive or deasserted) if not driven by any device         SONY VGP-BPS21A/B Battery ,

but the PCI bus does not depend on the resistors to change the signal level; all devices drive the signals high for one cycle before ceasing to drive the signals.

Signal timing

All PCI bus signals are sampled on the rising edge of the clock       SONY VGP-BPS21/S Battery .

Signals nominally change on the falling edge of the clock, giving each PCI device approximately one half a clock cycle to decide how to respond to the signals it observed on the rising edge, and one half a clock cycle to transmit its response to the other device.

The PCI bus requires that every time the device driving a PCI bus signal changes, one turnaround cycle must elapse between the time the one device stops driving the signal and the other device starts        SONY VGP-BPS21B Battery .

Without this, there might be a period when both devices were driving the signal, which would interfere with bus operation.

The combination of this turnaround cycle and the requirement to drive a control line high for one cycle before ceasing to drive it means that each of the main control lines must be high for a minimum of two cycles when changing owners    SONY VGP-BPS21A Battery .

The PCI bus protocol is designed so this is rarely a limitation; only in a few special cases (notably fast back-to-back transactions) is it necessary to insert additional delay to meet this requirement.


Any device on a PCI bus that is capable of acting as a bus master may initiate a transaction with any other device   SONY VGP-BPS21 Battery .

To ensure that only one transaction is initiated at a time, each master must first wait for a bus grant signal, GNT#, from an arbiter located on the motherboard. Each device has a separate request line REQ# that requests the bus, but the arbiter may "park" the bus grant signal at any device if there are no current requests       Sony VGP-BPS21A/B Battery .

The arbiter may remove GNT# at any time. A device which loses GNT# may complete its current transaction, but may not start one (by asserting FRAME#) unless it observes GNT# asserted the cycle before it begins        Sony VGP-BPS21/S Battery .

The arbiter may also provide GNT# at any time, including during another master's transaction. During a transaction, either FRAME# or IRDY# or both are asserted; when both are deasserted, the bus is idle. A device may initiate a transaction at any time that GNT# is asserted and the bus is idle       Sony VGP-BPS21A Battery .

Address phase

A PCI bus transaction begins with an address phase. The initiator, seeing that it has GNT# and the bus is idle, drives the target address onto the AD[31:0] lines, the associated command (e.g. memory read, or I/O write) on the C/BE[3:0]# lines, and pulls FRAME# low  Sony VGP-BPS21 Battery .

Each other device examines the address and command and decides whether to respond as the target by asserting DEVSEL#. A device must respond by asserting DEVSEL# within 3 cycles. Devices which promise to respond within 1 or 2 cycles are said to have "fast DEVSEL" or "medium DEVSEL", respectively        Sony Vaio PCG-5G2L Battery .

(Actually, the time to respond is 2.5 cycles, since PCI devices must transmit all signals half a cycle early so that they can be received three cycles later.)

Note that a device must latch the address on the first cycle; the initiator is required to remove the address and command from the bus on the following cycle, even before receiving a DEVSEL# response    Sony Vaio PCG-5G3L Battery .

The additional time is available only for interpreting the address and command after it is captured.

On the fifth cycle of the address phase (or earlier if all other devices have medium DEVSEL or faster), a catch-all "subtractive decoding" is allowed for some address ranges       Sony Vaio PCG-5J1L Battery .

This is commonly used by an ISA bus bridge for addresses within its range (24 bits for memory and 16 bits for I/O).

On the sixth cycle, if there has been no response, the initiator may abort the transaction by deasserting FRAME#. This is known as master abort termination and it is customary for PCI bus bridges to return all-ones data (0xFFFFFFFF) in this case   Sony Vaio PCG-5K2L Battery .

PCI devices therefore are generally designed to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.

Address phase timing

On the rising edge of clock 0, the initiator observes FRAME# and IRDY# both high, and GNT# low, so it drives the address, command, and asserts FRAME# in time for the rising edge of clock 1         Sony Vaio PCG-5J2L Battery .

Targets latch the address and begin decoding it. They may respond with DEVSEL# in time for clock 2 (fast DEVSEL), 3 (medium) or 4 (slow). Subtractive decode devices, seeing no other response by clock 4, may respond on clock 5. If the master does not see a response by clock 5, it will terminate the transaction and remove FRAME# on clock 6      Sony Vaio PCG-5K1L Battery .

TRDY# and STOP# are deasserted (high) during the address phase. The initiator may assert IRDY# as soon as it is ready to transfer data, which could theoretically be as soon as clock 2.

Dual-cycle address

To allow 64-bit addressing, a master will present the address over two consecutive cycles      Sony Vaio PCG-5L1L Battery .

First, it sends the low-order address bits with a special "dual-cycle address" command on the C/BE[3:0]#. On the following cycle, it sends the high-order address bits and the actual command. Dual-address cycles are forbidden if the high-order address bits are zero, so devices which do not support 64-bit addressing can simply not respond to dual cycle commands     Sony Vaio PCG-6S2L Battery .

Configuration access

Addresses for PCI configuration space access are decoded specially. For these, the low-order address lines specify the offset of the desired PCI configuration register, and the high-order address lines are ignored. Instead, an additional address signal, the IDSEL input, must be high before a device may assert DEVSEL#        Sony Vaio PCG-6S3L Battery .

Each slot connects a different high-order address line to the IDSEL pin, and is selected using one-hot encoding on the upper address lines.

Data phases

After the address phase (specifically, beginning with the cycle that DEVSEL# goes low) comes a burst of one or more data phases  Sony Vaio PCG-6V1L Battery .

In all cases, the initiator drives active-low byte select signals on the C/BE[3:0]# lines, but the data on the AD[31:0] may be driven by the initiator (in case of writes) or target (in case of reads).

During data phases, the C/BE[3:0]# lines are interpreted as active-low byte enables        Sony Vaio PCG-6W1L Battery .

In case of a write, the asserted signals indicate which of the four bytes on the AD bus are to be written to the addressed location. In the case of a read, they indicate which bytes the initiator is interested in. For reads, it is always legal to ignore the byte enable signals and simply return all 32 bits      Sony Vaio PCG-6W2L Battery ;

cacheable memory resources are required to always return 32 valid bits. The byte enables are mainly useful for I/O space accesses where reads have side effects.

A data phase with all four C/BE# lines deasserted is explicitly permitted by the PCI standard, and must have no effect on the target (other than to advance the address in the burst access in progress)       Sony Vaio PCG-6W3L Battery .

The data phase continues until both parties are ready to complete the transfer and continue to the next data phase. The initiator asserts IRDY# (initiator ready) when it no longer needs to wait, while the target asserts TRDY# (target ready). Whichever side is providing the data must drive it on the AD bus before asserting its ready signal         Sony Vaio PCG-7111L Battery .

Once one of the participants asserts its ready signal, it may not become un-ready or otherwise alter its control signals until the end of the data phase. The data recipient must latch the AD bus each cycle until it sees both IRDY# and TRDY# asserted, which marks the end of the current data phase and indicates that the just-latched data is the word to be transferred  Sony Vaio PCG-7112L Battery .

To maintain full burst speed, the data sender then has half a clock cycle after seeing both IRDY# and TRDY# asserted to drive the next word onto the AD bus.

This continues the address cycle illustrated above, assuming a single address cycle with medium DEVSEL, so the target responds in time for clock 3         Sony Vaio PCG-7113L Battery .

However, at that time, neither side is ready to transfer data. For clock 4, the initiator is ready, but the target is not. On clock 5, both are ready, and a data transfer takes place (as indicated by the vertical lines). For clock 6, the target is ready to transfer, but the initator is not      Sony Vaio PCG-7133L Battery .

On clock 7, the initiator becomes ready, and data is transferred. For clocks 8 and 9, both sides remain ready to transfer data, and data is transferred at the maximum possible rate (32 bits per clock cycle)          Sony Vaio PCG-7Z2L Battery .

In case of a read, clock 2 is reserved for turning around the AD bus, so the target is not permitted to drive data on the bus even if it is capable of fast DEVSEL.

Fast DEVSEL# on reads

A target that supports fast DEVSEL could in theory begin responding to a read the cycle after the address is presented  Sony Vaio PCG-8Y1L Battery .

This cycle is, however, reserved for AD bus turnaround. Thus, a target may not drive the AD bus (and thus may not assert TRDY#) on the second cycle of a transaction. Note that most targets will not be this fast and will not need any special logic to enforce this condition         Sony Vaio PCG-8Y2L Battery .

Ending transactions

Either side may request that a burst end after the current data phase. Simple PCI devices that do not support multi-word bursts will always request this immediately. Even devices that do support bursts will have some limit on the maximum length they can support, such as the end of their addressable memory         Sony Vaio PCG-8Z1L Battery .

Initiator burst termination

The initiator can mark any data phase as the final one in a transaction by deasserting FRAME# at the same time as it asserts IRDY#. The cycle after the target asserts TRDY#, the final data transfer is complete, both sides deassert their respective RDY# signals, and the bus is idle again         Sony Vaio PCG-8Z2L Battery .

The master may not deassert FRAME# before asserting IRDY#, nor may it deassert FRAME# while waiting, with IRDY# asserted, for the target to assert TRDY#.

The only minor exception is a master abort termination, when no target responds with DEVSEL#        Sony VAIO PCG-5G2L Battery .

Obviously, it is pointless to wait for TRDY# in such a case. However, even in this case, the master must assert IRDY# for at least one cycle after deasserting FRAME#. (Commonly, a master will assert IRDY# before receiving DEVSEL#, so it must simply hold IRDY# asserted for one cycle longer.)        Sony VAIO PCG-5G3L Battery

This is to ensure that bus turnaround timing rules are obeyed on the FRAME# line.

Target burst termination

The target requests the initiator end a burst by asserting STOP#. The initiator will then end the transaction by deasserting FRAME# at the next legal opportunity; if it wishes to transfer more data, it will continue in a separate transaction       Sony VAIO PCG-5J1L Battery .

There are several ways for the target to do this:

Disconnect with data

If the target asserts STOP# and TRDY# at the same time, this indicates that the target wishes this to be the last data phase  Sony VAIO PCG-5K2L Battery .

For example, a target that does not support burst transfers will always do this to force single-word PCI transactions. This is the most efficient way for a target to end a burst.

Disconnect without data

If the target asserts STOP# without asserting TRDY#, this indicates that the target wishes to stop without transferring data   Sony VAIO PCG-5J2L Battery .

STOP# is considered equivalent to TRDY# for the purpose of ending a data phase, but no data is transferred.


A Disconnect without data before transferring any data is a retry, and unlike other PCI transactions, PCI initiators are required to pause slightly before continuing the operation. See the PCI specification for details       Sony VAIO PCG-5K1L Battery .

Target abort

Normally, a target holds DEVSEL# asserted through the last data phase. However, if a target deasserts DEVSEL# before disconnecting without data (asserting STOP#), this indicates a target abort, which is a fatal error condition. The initiator may not retry, and typically treats it as a bus error      Sony VAIO PCG-5L1L Battery .

Note that a target may not deassert DEVSEL# while waiting with TRDY# or STOP# low; it must do this at the beginning of a data phase.

There will always be at least one more cycle after a target-initiated disconnection, to allow the master to deassert FRAME#   Sony VAIO PCG-6S2L Battery .

There are two sub-cases, which take the same amount of time, but one requires an additional data phase:


If the initiator observes STOP# before asserting its own IRDY#, then it can end the burst by deasserting FRAME# at the end of the current data phase       Sony VAIO PCG-6S3L Battery .


If the initiator has already asserted IRDY# (without deasserting FRAME#) by the time it observes the target's STOP#, it is already committed to an additional data phase. The target must wait through an additional data phase, holding STOP# asserted without TRDY#, before the transaction can end        Sony VAIO PCG-6V1L Battery .

If the initiator ends the burst at the same time as the target requests disconnection, there is no additional bus cycle.

Burst addressing

For memory space accesses, the words in a burst may be accessed in several orders. The unnecessary low-order address bits AD[1:0] are used to convey the initiator's requested order        Sony VAIO PCG-6W1L Battery .

A target which does not support a particular order must terminate the burst after the first word. Some of these orders depend on the cache line size, which is configurable on all PCI devices.

PCI burst ordering

A[1]  A[0]  Burst order (with 16-byte cache line)

0       0       Linear incrementing (0x0C, 0x10, 0x14, 0x18, 0x1C, ...)         Sony VAIO PCG-6W2L Battery

0       1       Cacheline toggle (0x0C, 0x08, 0x04, 0x00, 0x1C, 0x18, ...)

1       0       Cacheline wrap (0x0C, 0x00, 0x04, 0x08, 0x1C, 0x10, ...)

1       1       Reserved (disconnect after first transfer)         Sony VAIO PCG-6W3L Battery

If the starting offset within the cache line is zero, all of these modes reduce to the same order.

Cache line toggle and cache line wrap modes are two forms of critical-word-first cache line fetching. Toggle mode XORs the supplied address with an incrementing counter. This is the native order for Intel 486 and Pentium processors     Sony VAIO PCG-7111L Battery.

It has the advantage that it is not necessary to know the cache line size to implement it.

PCI version 2.1 obsoleted toggle mode and added the cache line wrap mode,  where fetching proceeds linearly, wrapping around at the end of each cache line      Sony VAIO PCG-7112L Battery .

When one cache line is completely fetched, fetching jumps to the starting offset in the next cache line.

Note that most PCI devices only support a limited range of typical cache line sizes; if the cache line size is programmed to an unexpected value, they force single-word access         Sony VAIO PCG-7113L Battery .

PCI also supports burst access to I/O and configuration space, but only linear mode is supported. (This is rarely used, and may be buggy in some devices; they may not support it, but not properly force single-word access either.)     Sony VAIO PCG-7Z1L Battery

Transaction examples

This is the highest-possible speed four-word write burst, terminated by the master:

On clock edge 1, the initiator starts a transaction by driving an address, command, and asserting FRAME# The other signals are idle (indicated by ^^^), pulled high by the motherboard's pull-up resistors       Sony VAIO PCG-7Z2L Battery .

That might be their turnaround cycle. On cycle 2, the target asserts both DEVSEL# and TRDY#. As the initiator is also ready, a data transfer occurs. This repeats for three more cycles, but before the last one (clock edge 5), the master deasserts FRAME#, indicating that this is the end        Sony VAIO PCG-8Y1L Battery .

On clock edge 6, the AD bus and FRAME# are undriven (turnaround cycle) and the other control lines are driven high for 1 cycle. On clock edge 7, another initiator can start a different transaction. This is also the turnaround cycle for the other control lines.

The equivalent read burst takes one more cycle, because the target must wait 1 cycle for the AD bus to turn around before it may assert TRDY#        Sony VAIO PCG-8Y2L Battery :

A high-speed burst terminated by the target will have an extra cycle at the end:

On clock edge 6, the target indicates that it wants to stop (with data), but the initiator is already holding IRDY# low, so there is a fifth data phase (clock edge 7), during which no data is transferred     WD passport essential (500GB/640GB) .


The PCI bus detects parity errors, but does not attempt to correct them by retrying operations; it is purely a failure indication. Because of this, there is no need to detect the parity error before it has happened, and the PCI bus actually detects it a few cycles later    WD passport essential (250GB/320GB) .

During a data phase, whichever device is driving the AD[31:0] lines computes even parity over them and the C/BE[3:0]# lines, and sends that out the PAR line one cycle later. All access rules and turnaround cycles for the AD bus apply to the PAR line, just one cycle later       WD  passport essential SE (750GB/1TB)       .

The device listening on the AD bus checks the received parity and asserts the PERR# (parity error) line one cycle after that. This generally generates a processor interrupt, and the processor can search the PCI bus for the device which detected the error.

The PERR# line is only used during data phases, once a target has been selected   WD  passport elite(250GB/320GB) .

If a parity error is detected during an address phase (or the data phase of a Special Cycle), the devices which observe it assert the SERR# (System error) line.

Even when some bytes are masked by the C/BE# lines and not in use, they must still have some defined value, and this value must be used to compute the parity     WD passport elite(500GB/640GB) .

Fast back-to-back transactions

Due to the need for a turnaround cycle between different devices driving PCI bus signals, in general it is necessary to have an idle cycle between PCI bus transactions. However, in some circumstances it is permitted to skip this idle cycle, going directly from the final cycle of one transfer    WD  passport studio for Mac(320GB/500GB) .

An initiator may only perform back-to-back transactions when:

they are by the same initiator (or there would be no time to turn around the C/BE# and FRAME# lines),the first transaction was a write (so there is no need to turn around the AD bus), and  the initiator still has permission (from its GNT# input) to use the PCI bus      WD  passport studio for Mac(500GB/640GB) .

Additional timing constraints may come from the need to turn around are the target control lines, particularly DEVSEL#. The target deasserts DEVSEL#, driving it high, in the cycle following the final data phase, which in the case of back-to-back transactions is the first cycle of the address phase     WD  Elements series(250GB/320GB) .

The second cycle of the address phase is then reserved for DEVSEL# turnaround, so if the target is different from the previous one, it must not assert DEVSEL# until the third cycle (medium DEVSEL speed).

One case where this problem cannot arise is if the initiator knows somehow (presumably because the addresses share sufficient high-order bits) that the second transfer is addressed to the same target as the previous one    WD  Elements SE(500GB/640GB) .

In that case, it may perform back-to-back transactions. All PCI targets must support this.

It is also possible for the target keeps track of the requirements. If it never does fast DEVSEL, they are met trivially. If it does, it must wait until medium DEVSEL time unless             WD Elements SE(750GB/1TB) :

the current transaction was preceded by an idle cycle (is not back-to-back), or

the previous transaction was to the same target, or

the current transaction began with a double address cycle          WD  Elements desktop(500GB/640GB) .

Targets which have this capability indicate it by a special bit in a PCI configuration register, and if all targets on a bus have it, all initiators may use back-to-back transfers freely.

A subtractive decoding bus bridge must know to expect this extra delay in the event of back-to-back cycles in order to advertise back-to-back support          WD  Elements desktop(750GB/1TB) .

64-bit PCI

This section explains only basic 64-bit PCI; the full PCI-X protocol extension is much more extensive.

The PCI specification includes optional 64-bit support. This is provided via an extended connector which provides the 64-bit bus extensions AD[63:32], C/BE[7:4]#, and PAR64   WD  Elements desktop(1.5 TB/2TB) .

Memory transactions between 64-bit devices may use all 64 bits to double the data transfer rate. Non-memory transactions (including configuration and I/O space accesses) may not use the 64-bit extension. During a 64-bit burst, burst addressing works just as in a 32-bit transfer, but the address is incremented twice per data phase       WD  passport essential SE (750GB/1TB)--USB 3.0)     .

The starting address must be 64-bit aligned; i.e. AD2 must be 0. The data corresponding to the intervening addresses (with AD2 = 1) is carried on the upper half of the AD bus.

To initiate a 64-bit transaction, the initiator drives the starting address on the AD bus and asserts REQ64# at the same time as FRAME#        WD  passport essential (500GB/640GB) .

If the selected target can support a 64-bit transfer for this transaction, it replies by asserting ACK64# at the same time as DEVSEL#. Note that a target may decide on a per-transaction basis whether to allow a 64-bit transfer.

If REQ64# is asserted during the address phase, the initiator also drives the high 32 bits of the address and a copy of the bus command on the high half of the bus         WD  passport for Mac(320GB/500GB) .

If the address requires 64 bits, a dual address cycle is still required, but the high half of the bus carries the upper half of the address and the final command code during both address phase cycles; this allows a 64-bit target to see the entire address and begin responding earlier        WD  passport for Mac(640GB/1TB) .

If the initiator sees DEVSEL# asserted without ACK64#, it performs 32-bit data phases. The data which would have been transferred on the upper half of the bus during the first data phase is instead transferred during the second data phase. Typically, the initiator drives all 64 bits of data before seeing DEVSEL#       My book essential 4 generation  (640GB/1TB) .

If ACK64# is missing, it may cease driving the upper half of the data bus.

The REQ64# and ACK64# lines are held asserted for the entire transaction save the last data phase, and deasserted at the same time as FRAME# and DEVSEL#, respectively       WD  My book essential 4 generation( 1.5TB/2TB) .

The PAR64 line operates just like the PAR line, but provides even parity over AD[63:32] and C/BE[7:4]#. It is only valid for address phases if REQ64# is asserted. PAR64 is only valid for data phases if both REQ64# and ACK64# are asserted.

Cache snooping (obsolete)

PCI originally included optional support for write-back cache coherence         WD  My book elite( 1TB/1.5TB) .

This required support by cacheable memory targets, which would listen to two pins from the cache on the bus, SDONE (snoop done) and SBO# (snoop backoff).

Because this was rarely implemented in practice, it was deleted from revision 2.2 of the PCI specification, and the pins re-used for SMBus access in revision 2.3        WD  My book studio(1TB/2TB) .

The cache would watch all memory accesses, without asserting DEVSEL#. If it noticed an access that might be cached, it would drive SDONE low (snoop not done). A coherence-supporting target would avoid completing a data phase (asserting TRDY#) until it observed SDONE high        WD  My book essential 4 generation( 1.5TB/2TB) .

In the case of a write to data that was clean in the cache, the cache would only have to invalidate its copy, and would assert SDONE as soon as this was established. However, if the cache contained dirty data, the cache would have to write it back before the access could proceed        WD  My book elite(640GB/2TB) .

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